1.1 Introduction to the course
Table of contents
The Universalization of IC Design from CASS (UNIC-CASS) program is an innovative initiative that offers a structured, end-to-end Integrated Circuit (IC) design-to-test experiential learning experience. The program’s primary goal is to enhance the know-how and accessibility to IC Design technologies for enthusiasts and design communities worldwide, particularly in low-to-middle-income and/or low-opportunity countries. It operates in strategic cooperation with the Solid-State Circuits Society, serving geographically-complementing locations. Participants, based on the quality of their submitted chip design proposals, will have the opportunity to learn from carefully curated materials, receive hands-on design mentoring by experts in the field, submit designs to CASS-sponsored fabrication runs via the Efabless chipIgnite program, and test their fabricated chip at selected testing facilities. This program provides a unique opportunity to gain hands-on design experience using open-source Electronic Design Automation (EDA) tools and Open PDKs.
Education is an essential part of UNIC-CASS. Therefore, this educational course has been created to help the UNIC-CASS participants design and implement integrated circuits from design to tape-out. It offers a jumpstart for the participants to get hands-on experience with open-source Electronic Design Automation (EDA) tools and Open PDKs.
They can learn from the video lectures with updated lecture notes for open-source design tools and Skywater 130nm PDK. These resources are carefully curated and regularly updated to ensure that participants have access to the most recent and relevant information along with the UNIC-CASS program.
One of the educational program’s key features is simplifying the opensource EDA tool & and PDK installation. The program provides detailed guidelines and support to help participants install and use the necessary tools and PDKs for designs and tape-outs with hand-on experience from the UNIC-CASS mentoring team. The participants in the program have the opportunity to submit their designs for fabrication through the Chip Ignite fabrication. This allows participants to see their designs come to life and provides invaluable practical experience.
The program also provides Guidelines & and design examples. These resources help participants understand the design process and provide inspiration for their own designs.
Finally, the UNIC-CASS education program offers a learning path for Digital and Analog/Mixed-signal design flow. This structured learning path helps participants comprehensively understand either digital or analog IC design flows. It guides participants through the process of designing their own chips, from initial concept to final testing.
Targeted audiences
This course is designed for people who already know how to design digital or analog/mixed-signal circuits and want to implement their circuits into silicon using open-source tools and open-source PDKs. The audience can quickly set up their design environment, start the design and evaluation process, and then implement it using the open-source PDKs. It will cover the schematic capture, symbol creation, transistor-level simulation, layout, design rule check, layout-versus-schematic, and parasitic extraction for analog/mixed-signal design flows while providing the instruction to simulate, synthesis, place-and-route, and sign-off (including design rule check, layout-versus-schematic and static timing check) for digital design flow. Most importantly, it provides an example of integrating the design into the caravel_user_project_wrapper so that the results can be fabricated in Open MPW or ChipIgnite program by Google and Efabless.
The course structure
The course is divided into seven parts. The first part introduces the courses, the targeted audience, the open-source PDKs, and the design flows for digital and analog designs. The second part focuses on the environment setup to quickly install the design tools and PDKs. After that, the third part details the analog design flow with schematic capture, symbol creation, simulation and debugging, design layout, design rule check, layout-versus-schematic check, and post-layout simulation. The fourth part and the fifth part are dedicated to digital design. The fourth part focuses on the caravel test harness and how to use the Openlane design flow to quickly implement your design into layouts to be fabricated in the Efabless ChipIgnite program or Google Open MPWs. The fifth part concerns the verification environment used in Caravel Test Harness, including functional verification, static timing check, physical verification, and sign-off. These steps are critical in a digital design before sending it to tape out. The sixth part is how to create a repository to submit the design to Efabless website to perform the pre-check and to run the tapeout jobs to ensure that the design conforms to the tapeout requirement and can be submitted for fabrication. Finally, some design examples are in the final part for both analog and digital design.
Learning path
| Digital design flow | Analog design flow |
|---|---|
| 1. Course introduction | |
| 2. Environment setup | |
| 2.1. Digital design tools on Linux or WSL using Docker |
2.2. Analog/Mixed-signal designs using Docker & remote desktop Or 2.3 Analog/Mixed-signal designs using Conda |
| 4. Digital design flow with openlane and caravel user project | 3. Analog design flow |
| 5. Functional verification in digital design flow | |
| 6. Preparing the design for tapeout | |
| 7. Design examples | |
| 7.1. Basic digital design with Caravel 7.6. OpenRAM compiler |
7.2 Comparator (Design & simulation) 7.3 Operational Amplifier (Layout) 7.4 Layout techniques in Magic |