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Table of contents

• 4.1 Openlane overview
• 4.2 Caravel test harness
• 4.3 Design setup using Caravel_user_project
• 4.4 Running example design from Caravel_user_project
• 4.5 How to integrate your own design
• 4.6 Running precheck and getting the design ready for tapeout
• 4.7 Synthesizing VHDL designs
• 4.8 Debug your run
• 5.1 Introduction to functional verification
• 5.2 RTL Verification & testing
• 5.3 Gate-level verification
• 5.4 Timing violations (setup, hold, recovery, removal)
• 5.5 Static timing analysis
• 5.6 Functional verification & STA in Cravel User Project wrapper