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Universalization of IC Design in CASS
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Course introduction
1.1 Introduction to the course
1.2 Introduction to PDKs
1.3 Introduction to the Digital Design Flow
1.4 Introduction to Analog Design Flow with opensource tools
Environment Setup
2.0 Prerequisites
2.1 Digital design tools on Linux or WSL using Docker
2.2 Analog Mixed Signal Design using docker image
2.3 Analog Mixed Signal Design tools on Linux or WSL using Conda
Analog Design Flow
3.1 Schematic capture and simulation with Xscheme and NGSpice
3.2 Spice Simulation using IHP SG13G2 PDK using Xscheme and NGSpice
3.3 Inverter Schematic and Simulation in Xscheme
3.4 Inverter's Subcircuit and Symbol in Xschem
3.5 Layout an Inverter in IHP SG13G2 with KLayout including DRC and LVS
3.6 Parasitic Extraction with Magic
3.7 Post-Layout Simulation
Digital Design Flow
4 Digital Design Implementation
5 Timing and verification
5.1 Introduction to functional verification
5.2 RTL Verification & testing
5.3 Gate-level verification
5.4 Timing violations (setup, hold, recovery, removal)
5.5 Static timing analysis
5.6 Functional verification & STA in Cravel User Project wrapper
Design examples
Skywater 130nm PDK
Course introduction
1.1 Introduction to the course
1.2 Introduction to PDKs
1.3 Introduction to the Digital Design Flow
1.4 Introduction to Analog Design Flow with opensource tools
Environment Setup
2.0 Prerequisites
2.1 Digital design tools on Linux or WSL using Docker
2.2 Analog Mixed Signal Design using docker image
2.3 Analog Mixed Signal Design tools on Linux or WSL using Conda
Analog Design Flow (Skywater 130nm PDK)
3.1 Schematic capture using Xschem & Circuit simulation using Ngspice
3.1.1 Basic schematic editing in Xschem and basic simulation using ngspice
3.1.2 View the simulation waveform in GAW
3.1.3 An inverter schematic in Xschem with Skywater 130nm
3.1.4 Symbol creation in Xschem
3.1.5 Hierarchical schematic captures in Xschem & time domain simulation
3.2 Design layout and design rule check with Magic
3.3 Design layout using Klayout
3.4 Design Rule check using KLayout
3.5 Layout-Versus-Schematic using Netgen
Digital Design Flow (Skywater 130nm PDK)
4.1 Openlane overview
4.2 Caravel test harness
4.3 Design setup using Caravel_user_project
4.4 Running example design from Caravel_user_project
4.5 How to integrate your own design
4.6 Running precheck and getting the design ready for tapeout
4.7 Synthesizing VHDL designs
4.8 Debug your run
5.1 Introduction to functional verification
5.2 RTL Verification & testing
5.3 Gate-level verification
5.4 Timing violations (setup, hold, recovery, removal)
5.5 Static timing analysis
5.6 Functional verification & STA in Cravel User Project wrapper
Preparing the design for tapeout
6.1 Caravel Overview
6.2 Setup your desktop
6.3 Creating a Repository
6.4 Cloning and Setup
6.5 Uploading your Design
6.6 Submitting Precheck and Tapeout Jobs
6.7 Creating an SSH Key
Design examples
7.1 A basic digital design using Caravel
7.2 Analog design of a comparator in Xschem & Ngspice
7.3 Analog layout of an Opamp
7.4 Layout techniques with magic
7.5 OSU Standard Cell design on Skywater 130nm
7.6 Openram
7.7 Xschem/NGSpice Monte Carlo Simulation
UNIC-CASS Homepage
Digital Design Flow
5 Timing and verification
5 Timing and Verification
Table of contents
5.1 Introduction to functional verification
5.2 RTL Verification & testing
5.3 Gate-level verification
5.4 Timing violations (setup, hold, recovery, removal)
5.5 Static timing analysis
5.6 Functional verification & STA in Cravel User Project wrapper