1.3 Introduction to the Digital Design Flow

The digital design flow, also known as the ASIC (Application-Specific Integrated Circuit) design flow, is a series of steps that an engineer follows to design and analyze a digital circuit. Here’s a high-level overview of the process:

  1. System Specification: The design process begins with a system specification, which defines the functionality, performance, physical, and electrical parameters of the circuit.
  2. Architectural Design: The system specification is converted into a detailed architecture. This includes defining the data path, control units, memory blocks, and other high-level components.
  3. RTL Coding: The architecture is then coded in a Hardware Description Language (HDL) such as Verilog or VHDL at the Register Transfer Level (RTL). This describes the flow of signals and the operation of the data path.
  4. RTL Verification: The RTL code is verified using simulation tools to ensure it meets the original specifications.
  5. Synthesis: The RTL code is converted into a gate-level representation using a synthesis tool. This process maps the RTL code to a specific technology library, which contains the logic gates and flip-flops used in the design.
  6. Gate-Level Verification: The gate-level netlist is verified using simulation tools to ensure it still meets the original specifications.
  7. Place and Route (P&R): The gate-level netlist is placed onto a chip and the interconnections are routed. This process also includes clock tree synthesis and power grid design.
  8. Physical Verification: The layout is checked for any violations of the design rules of the fabrication process. This includes Design Rule Checking (DRC) and Layout Versus Schematic (LVS) checks.
  9. Timing Analysis: The design is checked to ensure that it meets the required timing constraints. This includes setup and hold time verification, as well as checking for any timing violations.
  10. Tape-out: Once the design has passed all checks, it is sent for manufacturing. This process is known as tape-out.

OpenLane is an automated, open-source digital design flow that facilitates the process of designing integrated circuits (ICs). It is a part of the OpenROAD project and is designed to carry out all ASIC implementation steps, from RTL (Register Transfer Level) all the way down to GDSII (Graphic Data System version II), a standard for data exchange of IC layout artwork.

OpenLane integrates several open-source tools such as OpenROAD, Yosys, Magic, and Netgen, along with custom methodology scripts for design exploration and optimization. This integration abstracts the various steps of silicon implementation, enabling users to harden their designs using simple configuration files.

There are two versions of OpenLane: OpenLane 1, a stable silicon implementation platform built entirely on open-source software, and OpenLane 2, a next-generation silicon implementation platform for highly-custom chips. OpenLane 1 offers a simple, Docker®-based installation and has enabled countless tape-outs for Efabless’s chipIgnite and Google’s Open MPW programs. On the other hand, OpenLane 2 allows users to write fully custom ASIC implementation steps or flows.

OpenLane is gaining popularity in the field of Electronic Design Automation (EDA) for its stability, flexibility, enhanced user experience, and customizability. It is particularly useful for researchers, students, and small-scale projects due to its cost-effectiveness and transparency.

The digital design flow using OpenLane EDA tools involves several stages, each of which utilizes different open-source tools integrated within OpenLane. Here’s a high-level overview of the process:

  1. RTL Synthesis: The design flow starts with RTL (Register Transfer Level) description in Verilog. This is synthesized to gate-level representations using the Yosys tool.
  2. Technology Mapping: The synthesized output is then technology-mapped using the ABC tool.
  3. Floorplanning: The floorplan of the design is created, which includes the core area, locations of pre-placed cells, and the power structure.
  4. Placement: The design’s standard cells are placed in the rows created during floorplanning. This is done using the OpenROAD app.
  5. Clock Tree Synthesis (CTS): A balanced clock tree is synthesized for the design to minimize clock skew across sequential elements. This is done using the TritonCTS tool.
  6. Routing: The placed design is routed using the FastRoute tool for global routing followed by detailed routing using the OpenROAD app.
  7. Signoff: Finally, the design is checked for any violations and corrected. This includes Design Rule Checking (DRC) using the Magic tool, Layout Versus Schematic (LVS) check using the Netgen tool, and timing analysis using the OpenSTA tool.

This flow is iterative, meaning that if the design fails at any stage, it is optimized and the flow is run again. OpenLane automates this entire process, making it easier for designers to go from RTL to GDSII with less manual intervention.

References

  1. Ahmed Ghazy, OpenLane: The Open-Source Digital ASIC Implementation Flow, 2020.
  2. Efabless, OpenLane Overview