6.1 Croc System-on-Chip Example
This tutorial does not work with the current UNIC-CASS ICDesign Docker image. You will need to follow the instruction to install conda and then install yosys, openroad, klayout, verilator in the docker image.
conda install -c unic-cass yosys verilator openroad klayout magic netgen
Check out the sourcecode
git clone https://github.com/pulp-platform/croc && cd croc curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh export BENDER=$PWD/bender make checkout
Run the simulation
make verilator
Run the synthesis using yosys
make yosys-flist make yosys
cass@unic-cass$ make yosys-flist bender script flist-plus -t asic -t ihp13 -t rtl -t synthesis -D VERILATOR=1 -D SYNTHESIS=1 -D COMMON_CELLS_ASSERTS_OFF=1 > croc.flist cass@unic-cass$ make yosys cd yosys && \ SV_FLIST="/home/cass/croc/croc.flist" \ TOP_DESIGN="croc_chip" \ TMP="/home/cass/croc/yosys/tmp" \ OUT="/home/cass/croc/yosys/out" \ REPORTS="/home/cass/croc/yosys/reports" \ yosys -c /home/cass/croc/yosys/scripts/yosys_synthesis.tcl \ 2>&1 | TZ=UTC gawk '{ print strftime("[%Y-%m-%d %H:%M %Z]"), $0 }' \ | tee "/home/cass/croc/yosys/croc_chip.log" \ | gawk -f /home/cass/croc/yosys/scripts/filter_output.awk; [2025-12-04 13:50 UTC] 0. Executing init_tech: load technology from Github PDK [2025-12-04 13:50 UTC] 1. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 2. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 3. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x64_c2_bm_bist_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 4. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 5. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_2048x64_c2_bm_bist_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 6. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_256x48_c2_bm_bist_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 7. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_256x64_c2_bm_bist_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 8. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 9. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 10. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_512x64_c2_bm_bist_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 11. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib [2025-12-04 13:50 UTC] 12. Executing Liberty frontend: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib [2025-12-04 13:50 UTC] 13. Executing SLANG frontend. [2025-12-04 13:50 UTC] Top level design units: [2025-12-04 13:50 UTC] croc_chip [2025-12-04 13:50 UTC] [2025-12-04 13:50 UTC] Build succeeded: 0 Error, 0 Warning [2025-12-04 13:50 UTC] [2025-12-04 13:50 UTC] 13.1. Executing UNDRIVEN pass. (resolve undriven signals) .... [2025-12-04 13:52 UTC] 50. Executing Verilog backend. [2025-12-04 13:52 UTC] 51. Executing SPLITNETS pass (splitting up multi-bit signals). [2025-12-04 13:52 UTC] 52. Executing SETUNDEF pass (replace undef values with defined constants). [2025-12-04 13:52 UTC] 53. Executing HILOMAP pass (mapping to constant drivers). [2025-12-04 13:52 UTC] 57. Executing Verilog backend.
Run the Place & Route using Openroad
make openroad
cass@unic-cass $ make openroad mkdir -p /home/cass/croc/openroad/save mkdir -p /home/cass/croc/openroad/reports mkdir -p /home/cass/croc/openroad/out echo cd /home/cass/croc/openroad && \ NETLIST="/home/cass/croc/yosys/out/croc_chip_yosys.v" \ TOP_DESIGN="croc_chip" \ PROJ_NAME="croc" \ SAVE="/home/cass/croc/openroad/save" \ REPORTS="/home/cass/croc/openroad/reports" \ PDK="/ihp13/pdk" \ QT_QPA_PLATFORM=$(if [ -z "$DISPLAY" ]; then echo "offscreen"; else echo "$QT_QPA_PLATFORM"; fi) \ openroad scripts/chip.tcl \ $(if [ "" = "1" ]; then echo "-gui"; fi) \ -log croc.log \ 2>&1 | TZ=UTC gawk '{ print strftime("[%Y-%m-%d %H:%M %Z]"), $0 }'; [2025-12-04 13:56 UTC] OpenROAD 2.0-24534-gd1d9c1518e [2025-12-04 13:56 UTC] Features included (+) or not (-): +GPU +GUI +Python [2025-12-04 13:56 UTC] This program is licensed under the BSD-3 license. See the LICENSE file for details. [2025-12-04 13:56 UTC] Components of this program may be licensed under more restrictive licenses which must be honored. [2025-12-04 13:56 UTC] Init tech from Github PDK [2025-12-04 13:56 UTC] Init standard cells [2025-12-04 13:56 UTC] Init IO cells [2025-12-04 13:56 UTC] Init SRAM macros [2025-12-04 13:56 UTC] Init tech-lef [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef, created 19 layers, 300 vias [2025-12-04 13:56 UTC] Init cell-lef [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef, created 78 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_io/lef/sg13g2_io.lef, created 22 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/bondpad/lef/bondpad_70x70.lef, created 1 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x16_c2_bm_bist.lef, created 1 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x64_c2_bm_bist.lef, created 1 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x8_c2_bm_bist.lef, created 1 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_2048x64_c2_bm_bist.lef, created 1 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_256x48_c2_bm_bist.lef, created 1 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_256x64_c2_bm_bist.lef, created 1 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_4096x16_c3_bm_bist.lef, created 1 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_4096x8_c3_bm_bist.lef, created 1 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_512x64_c2_bm_bist.lef, created 1 library cells [2025-12-04 13:56 UTC] [INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_64x64_c2_bm_bist.lef, created 1 library cells [2025-12-04 13:56 UTC] ############################################################################### [2025-12-04 13:56 UTC] # Step 00: Initialization [2025-12-04 13:56 UTC] ############################################################################### ....
Run the klayout to generate the GDSII
make klayout